1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a capacitor in a semiconductor device and a method of fabricating a capacitor suitable for a highly-integrated memory device using a TaON dielectric layer having a high dielectric constant.
2. Background of the Related Art
As the degree of integration of memory products increases with the development of fine linewidth semiconductor technology, the unit memory cell area has been greatly reduced and the operating voltages have been decreased.
In spite of this reduction in cell area, the charging capacitance necessary for proper memory device operation has remained at least 25 fF/cell so as to prevent the generation of soft errors and avoid the need to reduce the refresh time.
In a conventional DRAM capacitor utilizing a nitride/oxide (xe2x80x9cNOxe2x80x9d)layer structure as a dielectric, the configuration of the lower electrode may be modified to provide a complex three-dimensional structure or increase the height of the lower electrode. These structural modifications serve to increase the effective surface area and thereby provide the necessary charge capacitance.
However, the range of three-dimensional lower electrode configurations is limited by process difficulties. Moreover, increasing the lower electrode height produces a step height difference between the cell areas and the peripheral circuit areas. Eventually, increasing the step height difference will degrade the yield and reliability of the resulting devices, as a result of difficulties in forming conductors due to difficulties in obtaining a sufficient depth of focus during subsequent photolithographic processes.
Therefore, capacitors having conventional NO dielectric structures cannot be manufactured with both sufficient charge capacitance and cell area required for next generation DRAM devices having 256M or more memory cells.
Lately, developments of Ta2O5 capacitors, which use Ta2O5 films having dielectric constants ranging 25 to 27, instead of NO films having dielectric constants ranging 4 to 5, have been made to overcome the short comings of NO capacitors.
Ta2O5 films, however, have an unstable chemical stoichiometric ratio, which results in Ta atoms in the film that are not fully oxidized due to differences in the composition ratio between the Ta and O atoms. Namely, it is inevitable that substitution type Ta atoms of an oxygen vacancy type exist locally in the film due to the unstable chemical composition ratio of the material itself.
Although the number and density of the oxygen vacancies in the Ta2O5 film may vary in accordance with the ratio of the components and their bonding degree, oxygen vacancies can not be avoided completely.
Therefore, in order to prevent current leakage of a capacitor, an additional oxidation process is required to oxidize the substitution type Ta atoms present in the dielectric film to produce a more stable stoichiometric ratio throughout the Ta2O5 film.
Moreover, the Ta2O5 film has a high oxidation reactivity with polysilicon and TiN, materials that are commonly used to form the upper and/or lower electrodes of the capacitor. This reaction tends to form a low dielectric oxide layer and greatly reduce the homogeneity at an interface as oxygen in the Ta2O5 film migrates to the interface and reacts with the electrode material.
Further, when the Ta2O5 film is formed, carbon atoms and carbon compounds such as CH4, C2H4 and the like, and H2O are produced by the reaction between the organic portions of the organometallic Ta(OC2H5)5 precursor and the O2 or N2O gas used to form the Ta2O5 film and are incorporated into the film as impurities.
Consequently, oxygen vacancies, as well as carbon atoms, ions, and radicals exist in the Ta2O5 film as impurities and increase the leakage current of the resulting capacitors and degrade their dielectric characteristics.
A proposed solution to these problems is a post-formation thermal treatment (oxidation) using an electrical furnace or RTP and a N2O or O2 ambient to overcome these problems.
However, the post-formation thermal treatment in the N2O or O2 ambient may increase the depth of the depletion layer since an oxide layer having a low dielectric constant is formed at the interface with the lower electrode.
Regarding the problems resulting from the post-formation thermal treatment and the subsequent formation of a contact plug for storing electric charges and a dielectric layer, a capacitor in a semiconductor device and a conventional method of fabrication are explained below with reference to FIGS. 1-3.
FIGS. 1 and 2 show cross-sectional views of a capacitor in a semiconductor device and a fabrication method thereof according to a conventional method.
Referring to FIG. 1, an insulating interlayer 3, a barrier nitride layer 5, and a buffer oxide layer 7 are sequentially deposited on a semiconductor substrate 1. In this case, the insulating interlayer 3 is preferably formed by depositing HDP, BPSG, or SOG materials. The barrier nitride layer 5 is preferably formed using a plasma nitride deposition and the buffer oxide layer 7 is preferably deposited using PE-TEOS.
An upper surface of the buffer oxide layer 7 is then coated with a photoresist pattern (not shown in the drawing) for a plug contact mask. Using the photoresist pattern as a mask, contact holes 9 are then formed by removing portions of the buffer oxide layer 7, the barrier nitride layer 5, and the insulating interlayer 3 to expose portions of the semiconductor substrate 1.
The photoresist pattern (not shown in the drawing) is then removed and a polysilicon material is deposited on the wafer. The polysilicon fills the contact holes 9 and forms a layer on the upper surface of the buffer oxide 7. Contact plugs 11 are then formed by selectively removing the polysilicon material from the buffer oxide 7 by blanket etch.
Referring to FIG. 2, a cap oxide layer 13 is then deposited on an exposed upper surface of the entire structure including the contact plugs 11.
After the cap oxide layer 13 has been coated with a photoresist pattern (not shown in the drawing) for a storage node mask, upper surfaces of the contact plugs 11 are exposed by selectively removing the cap oxide layer 13 using the photoresist pattern as an etch mask.
A doped polysilicon layer 15 is then deposited on the exposed surface of the cap oxide layer 13 and the exposed upper surface of the contact plugs 11.
Referring to FIG. 2, lower electrodes 15a are formed by selectively removing the doped polysilicon layer 15 with blanket etch until the cap oxide layer 13 is exposed. A TaON or Ta2O5 dielectric layer 17 is then formed on an upper surface of the entire structure including the lower electrodes 15a. 
A thermal treatment is then performed on the TaON or Ta2O5 dielectric layer 17 in an ambient of N2O or O2.
Finally, an upper electrode 19 is formed on the TaON or Ta2O5 dielectric layer 17 to complete the capacitor fabrication.
As mentioned above, the contact plug 11 for a lower electrode contact in a capacitor in a semiconductor device using a TaON or Ta2O5 dielectric as shown in FIG. 1, is formed by sequentially depositing the insulating interlayer (an oxide layer existing between the bit lines and the lower electrodes, which is not shown in the drawing), a barrier nitride layer, and an oxide buffer layer. These layers are then selectively removed to form an opening, a layer of conductive material is deposited, and the portion of the conductive layer that is not inside the opening removed area is removed to leave contact plugs.
Unfortunately, when the contact plugs are formed in such a manner, as shown in FIG. 2, the contact plugs 11 protrude out over the barrier nitride layer 5 by about 500 to 1500 xc3x85. This tends to reduce the area occupied by the lower electrodes and cause electrical degradation and reliability problems as a result of the increased probability of generating bridges between adjacent contact plugs.
Further, the depletion layer becomes deeper since an oxide layer having a low dielectric constant is formed at the interface between the lower electrodes and the dielectric layer during the subsequent thermal treatment in the N2O or O2 ambient on the TaON or Ta2O5 dielectric layer.
Thus, the efficiency of the capacitor is reduced as a depletion ratio (C) ranges from about 7 to 17%.
In this case, the depletion ratio (C)=1xe2x88x92{(Cmaxxe2x88x92Cmin)/Cmax}xc3x97100, where Cmax is a capacitance Cs when xe2x80x9c+xe2x80x9d voltage is applied to the upper electrode and Cmin is a capacitance Cs when xe2x80x9cxe2x88x92xe2x80x9d voltage is applied to the upper electrode.
In the fabrication method of TaON capacitor in the related art, thermal treatment is carried out in a N2O or O2 ambient at a temperature of 700 to 800xc2x0 C. after deposition of the TaON film so as to remove the oxygen vacancies and carbon impurities in the film that would result in leakage current in the capacitor.
Unfortunately, during such thermal treatment, a portion of the nitrogen, which comprise as much as 20 to 30% of the TaON film, migrate to the surface of the polysilicon layer forming the lower electrode so as to be piled up while a portion of the nitrogen components diffuse outside so as to cause dielectric loss, thereby failing to provide sufficient and large charge capacitance.
Accordingly, the present invention is directed to a capacitor for a semiconductor device and a method for fabricating such capacitors that substantially eliminates or overcomes one or more of the problems, limitations, and disadvantages of the prior art methods and devices.
The object of the present invention is to provide a capacitor for a semiconductor device and a fabrication method that reduces or eliminates reduced product cost by decreasing both the number of unit processes and total processing time necessary to form a contact plug.
Another object of the present invention is to provide a capacitor for a semiconductor device and a method of fabricating such capacitors that reduces or eliminates the generation of bridges between adjacent contact plugs to improve the yield and reliability of the resulting semiconductor device.
A further object of the present invention is to provide a capacitor for a semiconductor device and a method of fabricating such capacitors that provide a high charge capacitance by minimizing the depletion ratio toward the lower electrode.
Another further object of the present invention is to provide a capacitor for a semiconductor device and a method of fabricating such capacitors that produces a capacitor suitable for a highly-integrated memory devices by increasing the dielectric constant of a TaON dielectric layer through subsequent thermal treatment or plasma annealing treatment.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims as well as illustrated in the referenced drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a method of fabricating a capacitor in a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate and forming a lower electrode having MPS (metastable polysilicon) on the semiconductor substrate. The lower electrode is then doped at a temperature 550 to 660xc2x0 C. in a phosphorus gas ambient, a TaON dielectric layer is formed on the lower electrode, and an upper electrode is formed on the TaON dielectric layer.
In another aspect, a method of fabricating a capacitor in a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate, forming an insulating interlayer on the semiconductor substrate wherein a contact hole is formed through the insulating interlayer. A contact plug is then formed in the contact hole and a lower electrode having MPS is then formed and electrically connected to the contact plug. The lower electrode is then doped at a temperature of 550 to 650xc2x0 C. in a phosphorus gas ambient, a TaON dielectric layer is formed on the lower electrode and annealed, and an upper electrode layer is formed on the TaON dielectric layer.
In a further aspect, a method of fabricating a capacitor in a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate, forming a first insulating interlayer having a first contact hole on the semiconductor substrate. A first contact plug is then formed in the first contact hole from doped polysilicon, an etch barrier layer is then formed on an upper surface of the first insulating interlayer and the contact plug, and a second insulating interlayer is formed on the etch barrier layer. A hard mask polysilicon layer and an anti-reflection layer are then formed on the second insulating interlayer and a second contact hole is formed to expose an upper surface of the contact plug by removing the overlaying anti-reflection layer, hard mask polysilicon layer, second insulating interlayer, and the etch barrier layer. A doped polysilicon layer is then formed on the anti-reflection layer and the exposed upper surface of the contact plug, an MPS (metastable polysilicon) layer is then formed on the doped polysilicon layer and thermally doped at a temperature of 550 to 660xc2x0 C. in a phosphorus gas ambient. A sacrificial layer is then formed to bury the MPS layer and an upper surface of the second insulating interlayer is then exposed by selectively removing the sacrificial layer, the MPS layer, the doped polysilicon layer, the anti-reflection layer, and the hard mask polysilicon layer, completely removing the remaining sacrificial layer, forming a TaON dielectric layer on the exposed surface of the second insulating interlayer and polysilicon layer of the MPS layer, carrying out a first annealing treatment on the TaON dielectric layer at a temperature of 700 to 900xc2x0 C. in an ambient of N2O or O2, forming an upper electrode on the TaON dielectric layer, and carrying out a second annealing treatment at a temperature of 800 to 950xc2x0 C. after forming the upper electrode.
In another further aspect, a capacitor in a semiconductor device according to the present invention includes a semiconductor substrate, a lower electrode on the semiconductor substrate, the lower electrode having an MPS layer that has undergone thermal doping treatment at a temperature of 550 to 660xc2x0 C. in a phosphorus gas ambient, a TaON dielectric layer formed on the lower electrode, and an upper electrode formed on the TaON dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.